The present invention concerns a semiconductor device and, more in particular, it relates to a technique which is effective to be applied to a semiconductor device having a power MISFET (Metal Insulator Semiconductor Field Effect Transistor).
Transistors that can be used for high power application of several watts or higher are referred to as power transistors, for which various structures have been studied.
Among them, power MISFETs includes those referred to as a vertical type and lateral type and they are classified structure, for example, into a trench type and planer type in accordance with the structure of a gate portion.
The MISFET described above has a structure in which plural MISFETs each of a fine pattern are connected (for example, by the number of several thousands) in parallel in order to cope with high power.
Barrier films (barrier metal films) are formed to connection portions with wirings or semiconductor substrates for preventing formation of undesired reaction layers or deposition of underlayer material caused by the contact of material constituting them.
For example, Japanese Patent Laid-Open No. 2001-127072 discloses a technique of forming titanium tungsten between source wirings (15) and a semiconductor substrate (1S) of a power MISFET.